1. Field of the Invention
The present invention relates to a semiconductor device having a low dielectric layer as an inter-layer insulating layer and method of manufacturing a semiconductor device having that structure, more particularly relates to technology for formation of multilayer interconnections able to be used for under 0.25 xcexcm rule device processes.
2. Description of the Related Art
Recently, increasingly fine interconnections and reduced interconnection pitches have been demanded along with the increasing miniaturization of semiconductor devices. Further, increasingly lower dielectric rates have been demanded for inter-layer insulating layers along with demands for lower power consumption and higher speeds. In particular, in logic type devices, a rise in resistance due to finer interconnections and an increase in the capacitance of the interconnections leads to a reduction in the speed of the device, so finer multilayer interconnections having low dielectric layers as inter-layer insulating layers have become essential.
Increasing finer interconnection widths and reduced pitches, however, not only increase the ratio of the length and width of the interconnections themselves, but also increase the aspect ratio of the spaces between the interconnections and, as a result, place an additional burden on the formation of longitudinally narrow, fine interconnections, the burying of the fine spaces between interconnections by inter-layer layers, etc. and therefore both complicate the process and increase the number of process steps.
To solve this problem, there is known the so-called xe2x80x9cdamascenexe2x80x9d process of simultaneously burying the contact holes and interconnection grooves by aluminum reflow sputtering and then smoothing the surface aluminum by chemical mechanical smoothing (CMP).
The damascene process does not require the forming of high aspect ratio aluminum interconnections by etching or burying of the narrow spaces between interconnections by an inter-layer insulating layer, so can greatly reduce the number of process steps. In this process, the higher the aspect ratio of interconnections and the greater the total number of interconnections, the greater the contribution to the reduction of the total cost. Further, reduction of the dielectric rate of the inter-layer insulating film can be expected to reduce the capacitance of the space between interconnections.
However, films comprised of materials with small dielectric constants differ tremendously in nature from the silicon oxide films used in conventional devices. No process technology has yet been developed for them. Therefore, practical technology for this is now being sought.
Further, in recent years, use of xerogel as a material in semiconductor devices is being closely examined as it promises a dielectric constant of less than 2.0.
In relation to this art, Japanese Unexamined Patent Publication (Kokai) No. 8-70005 discloses a structure, as shown in FIG. 9, providing dummy leads 93 for dispersing heat in a low dielectric material 96 as a method of increasing the reliability of metal leads 94. This structure is comprised of a substrate 92 on which are provided metal leads 94 made of an aluminum alloy etc., a low dielectric material 96 comprised of a space, silica-airogel, organic SOG, fluorine doped silicon oxide, etc. at least between the metal leads 94, a heat conductive insulating layer 97 comprised of a laminate of AlN, Si3N44, and AlN deposited on the metal leads 94 and the low dielectric material 96, and dummy leads 93 comprised of an aluminum alloy etc. adjacent to the metallic leads 94.
In this structure, the heat from the metal leads 94 can move to the dummy leads 93 which are able to disperse the heat and to the heat conductive insulating layer 97 which is made of an insulating material such as AlN having a heat conductivity 20% higher than the low dielectric material, preferably a heat conductivity 20% higher than that of Si3N4. By structuring the device in this way, it is possible to reduced the interconnection capacitance between lines (or leads) and, along with the fall in the heat conductivity of the low dielectric material, prevent damage to the metal leads by the Joule""s heat effect, which becomes a problem when using metal leads with a high aspect ratio, and thereby obtain a semiconductor device having more reliable metal leads.
Turning now to the problems to be solved by the present invention, the above-mentioned damascene method forms the interconnection layer in advance on the inter-layer insulating layer, then buries this with a metal and polishes the metal by CMP to form the interconnections. With conventional inter-layer insulating layers, use has been made of an inorganic material such as a silicon oxide film. Use is now however being made of materials with low dielectric rates with the object of suppressing an increase in capacitance along with miniaturization. Most materials with low dielectric rates are organic. Organic films have a hardness of {fraction (1/10)} to {fraction (1/100)} that of the conventional silicon oxide and other inorganic films and therefore lack the hardness required for the damascene process.
That is, most substances with low dielectric constants, in particular low dielectric films with dielectric constants less than 3, are also organic. Organic films are softer than the silicon oxide films used for conventional inter-layer insulating layers. For example, compared by Young""s modules, a silicon oxide has a value of 5xc3x971010, while a resin used for an organic film has a small value of 0.3 to 0.8xc3x971010.
Therefore, when forming interconnections by the damascene method, many scratches are formed on the organic film. These scratches cause lower product yield. Therefore, the general practice has been to form a silicon oxide layer or nitride layer on the organic film, but these layers have a higher dielectric rate than the organic film, so there was the problem that the capacitance between interconnections ended up increasing.
Therefore, the idea has been proposed of making joint use of a silicon oxide film and a silicon nitride film at the time of the damascene process. These films, however, have high dielectric rates and therefore had the problem of halving the effect of reduction of the dielectric rate by the organic film.
Further, an organic film has a very small heat conductivity of about {fraction (1/10)} that of the inter-layer insulating layer (silicon oxide layer) used for conventional semiconductor devices and therefore had a serious effect on the dispersion of the heat of the elements. That is, while the amount of heat generated per unit area falls along with the reduction in size of a device, the heat conductivity of the paths for radiation of that heat has been falling as well.
Therefore, a structure of a device giving due consideration to the paths for heat dispersion is desired.
Xerogel is a well-known substance, for example, used as a desiccant under the name of xe2x80x9csilica gelxe2x80x9d. Use for a semiconductor device however would be difficult as things now stand due to the various requirements on reliability. That is, xerogel is comprised of 50% to 90% by volume and therefore suffers from problems in mechanical strength, heat conductivity, heat resistance, moisture resistance, inter-layer adhesion, etc.
Accordingly, a structure of a device which solves the above mentioned problem and enables use of xerogel with its low dielectric constant is desired.
An object of the present invention is to provide a semiconductor device using a low dielectric film as an inter-layer insulating layer and a method of manufacturing the same.
The present inventors, in consideration of the above problems, invented a semiconductor device having an organic layer as a low dielectric layer or an organic layer containing xerogel as an inter-layer insulating layer and formed by the damascene method and a method of manufacturing the same.
That is, according to the present invention, there is provided a semiconductor device having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a first dielectric layer having a dielectric constant of not more than 3.0, and an interconnection layer formed in the dielectric layer in contact with the insulating layer, wherein the upper surface of the interconnection layer is higher than the upper surface of the dielectric layer.
The present invention also provides a method of manufacturing a semiconductor device which has the steps of forming an insulating layer on a semiconductor substrate, forming a dielectric layer having a dielectric constant of not more than 3.0 on the insulating layer, forming an inorganic layer on the dielectric layer, forming a pattern on the dielectric layer for forming an interconnection, forming an interconnection layer over the entire surface, smoothing the interconnection layer, and removing the inorganic layer.
In the semiconductor device and method of manufacturing the same of the present invention, the dielectric layer is preferably an organic layer comprised of at least one material selected from the group comprising a cyclic fluororesin, polytetrafluoroethylene, a fluorinated ethylene propylene, a copolymer of tetrafluoroethylene and perfluoroalkoxyethylene, polyfluorovinylidene, polytrifluorochloroethylene, a fluoroaryl ether resin, polyfluoroimide, benzocyclobutene (BCB) polymer, polyimide, amorphous carbon, a monomethyltrihydroxysilane (organic SOG) condensate, a polymer having a repeating structural unit in its molecule of: 
where, m and n each represents a natural number,
a polymer having a repeating structural unit in its molecule of 
where, x, y and z each represents a natural number,
a polymer having a repeating structural unit in its molecule of 
where, R represents an alkylene or a phenylene group,
and a polymer having a repeating structural unit in its molecule of 
where, Rxe2x80x2 represents an alkylene or a phenylene group,
Additionally, the above low dielectric layer may be made of material available commercially under the brand names Amorphous Teflon, CYTOP (phonetic), and Flare.
The semiconductor device of the present invention preferably has a dummy interconnection at a portion of an interconnection space of at least three times the pitch in the interconnection pattern, more preferably so all of the interconnection spaces are not more than 1 xcexcm.
The semiconductor device of the present invention preferably has an inter-layer insulating layer containing xerogel on the dielectric layer, more preferably has a layer containing a silane coupling agent on the inter-layer insulating layer containing xerogel.
Further, the semiconductor device preferably has a dummy contact hole in the insulating layer under the dummy interconnection not connected with a lower conductive layer.
As the lower conductive layer, an impurity diffusion region provided in the semiconductor substrate or a lower interconnection layer may be mentioned.
In the method of manufacturing a semiconductor device of the present invention, the inorganic layer is preferably a layer comprised of at least one material selected from the group consisting of a silicon oxide, fluorine doped silicon oxide, silicon nitride, silicon oxynitride, a silanol condensate (inorganic SOG), phosphorus-doped silicon oxide, boron-doped silicon oxide, and boron-phosphorus-doped silicon oxide.
The method of manufacturing a semiconductor device of the present invention preferably has a step of forming a dummy interconnection at a portion of an interconnection space of at least three times the pitch in the interconnection pattern, more preferably so all of the interconnection spaces are not more than 1 xcexcm.
The step of forming the dummy interconnection preferably is a step of simultaneously forming a pattern for forming an interconnection and for forming a dummy interconnection in a portion of an interconnection space of at least three times the pitch in the interconnection pattern, more preferably so all of the interconnection spaces are not more than 1 xcexcm.
The step of smoothing the interconnection layer is preferably a step of smoothing by CMP.
As explained in detail above, the present invention relates to a semiconductor device having an organic layer having a low dielectric constant or xerogel formed by the damascene method and a method of manufacturing the same.
The damascene method forms the interconnection pattern in advance on an inter-layer insulating layer, buries this with a metal, then uses CMP (chemical mechanical smoothing) to polish the metal and form the interconnection layer.
Until now, hard materials such as silicon oxide have been used for inter-layer insulating layers. Organic layers are now however coming into use as low dielectric materials for the purpose of suppressing the increase in capacitance accompanying the increasing miniaturization of semiconductor devices.
However, organic layers differ tremendously in nature from inorganic layers of silicon oxide etc. For example, they lack the hardness necessary for the damascene process. The value is said to be {fraction (1/10)} to {fraction (1/100)} the same. Therefore, in the present invention, it was conceived to first form an inorganic layer on the organic layer, then form the interconnection layer in the organic layer by the damascene method and then remove the inorganic layer.
On the other hand, an organic layer has a low heat conductivity, so the dispersion of the heat at the time of operation of the device became a problem. Therefore, in the present invention, a method of manufacturing a semiconductor device including forming a path for radiating the heat, that is, a dummy interconnection, by the damascene method in the process for formation of interconnections was devised.
Further, the present invention proposes a new structure for increasing the heat radiating effect by forming a dummy contact hole under the dummy interconnection not connected with the lower conductive layer when forming contact holes for connecting the lower conductive layer and upper interconnections.
Further, the present invention conceived of application of a xerogel layer, now being researched as a low dielectric layer, to the process of formation of interconnections. A xerogel layer is a low dielectric layer, but is inferior to conventional inter-layer insulating layers in terms of mechanical strength, heat conductivity, adhesion, waterproofness, etc. Therefore, in the present invention, the structure was devised of reducing the locations of use of the xerogel as much as possible and combining a low dielectric layer with an inorganic insulating layer so as to reduce the capacitance between interconnections without detracting from the effect of the low dielectric layer. That is, xerogel is used only at parts where the interconnection capacitance would become the greatest, while an other low dielectric layers than xerogel are used at other locations.
In addition, in consideration of the fact that a xerogel layer is inferior in inter-layer adhesion, the present invention proposes providing a film formed from a silane coupling agent below and/or above the xerogel layer.
According to the present invention, since the inter-layer insulating layer is made of a dielectric layer having a dielectric constant of not more than 3.0 (hereinafter referred to as a xe2x80x9clow dielectric layerxe2x80x9d), it is possible to manufacture a miniature semiconductor device where the increase in capacitance between interconnections is greatly suppressed.
Further, when providing a dummy interconnection for radiating heat at a portion of an interconnection space of at least three times the pitch in the interconnection pattern, it is possible to effectively prevent a reduction in the heat dispersion efficiency due to the use of a low dielectric layer with a small heat conductivity.
When providing a dummy contact hole under the dummy interconnection layer, it is possible to further improve the heat dispersion effect.
Further, according to the present invention, by using a layer containing xerogel, with its extremely small dielectric constant, around an interconnection (left and right of interconnection), preferably at locations of an interconnection space not more than three times the standard pitch, and by using a low dielectric layer around a contact hole between interconnections (above and below interconnection layers), it is possible to cover up defects in the xerogel layer and greatly reduce the interconnection capacitance and therefore possible to manufacture a highly reliable semiconductor device of a miniature structure with a good product yield.
Further, by providing a layer comprised of a silane coupling agent above and below the layer containing xerogel, it is possible to manufacture a semiconductor device superior in inter-layer adhesion.